The present invention generally relates to semiconductor integrated circuit devices, and more particularly to a semiconductor integrated circuit device having a gate array and a memory and provided with a function of testing the memory.
In order to improve the reliability of the semiconductor integrated circuit device, the manufacturer of the semiconductor integrated circuit device tests the memory thereof before forwarding the semiconductor integrated circuit device to the user. Hence, the semiconductor integrated circuit device is provided with a memory testing circuit for testing the memory of the semiconductor integrated circuit. It is also possible for the user to test the memory by use of the memory testing circuit, and further, the memory testing circuit can in some cases be used to totally clear the contents of the memory.
When providing such a memory testing circuit in the semiconductor integrated circuit devices, it is desirable that the number of input/output pins for supporting the memory testing function is extremely small and that an interconnection (or wiring) region is effectively utilized without the need to draw the interconnection around wastefully.
FIG.1 generally shows the conventional semiconductor integrated circuit device having the memory testing function. The semiconductor integrated circuit device comprises gate arrays 1 and 2, a random access memory (RAM) 3, normal signal input terminals 4, test signal input terminals 5, and output terminals 6. There are two kinds of interconnection coupling the gate array 1, the RAM 3 and the gate array 2, namely, a first interconnection of a normal signal system and a second interconnection of a test signal system. Both the first and second interconnections are formed during an interconnection pattern forming process by automatically designing the interconnection layout pattern using the computer aided design (CAD) technique. In other words, both the first and second interconnections are designed for each kind or model of the semiconductor integrated circuit device depending on a logic circuit constituted by the gate array.
In a normal mode, normal signals such as an address signal, a block select signal, a write-enable signal and a normal input data are supplied to the normal signal input terminals 4. The normal input data is supplied to the RAM 3 through the gate array 1 and is written into a memory cell array of the RAM 3 responsive to the write-enable signal from a block selected by the block select signal. A normal output data read out from the RAM 3 is obtained through the gate array 2 and is outputted from the output terminals 6.
In a test mode, test signals such as an address signal, a block select signal, a write-enable signal and a test input data are supplied to the test signal input terminals 5. The test input data are supplied to the RAM 3 through the gate array 1 and is written into memory cell array of the RAM 3 responsive to the write-enable signal from a block selected by the block select signal. A test output data read out from the RAM 3 is obtained through the gate array 2 and is outputted from the output terminals 6. It is impossible to check the state of the RAM 3 from the test output data outputted from the output terminals 6.
According to this conventional semiconductor integrated circuit device, the normal signal input terminals 4 and the test signal input terminals 5 are provided independently, thereby resulting in a large number of input/output pins. For this reason, the number of input/output pins originally for use with the gate array is reduced because of the need to provide independent input/output pins for supporting the memory testing function. Hence, there is a problem in that the gate arrays 1 and 2 cannot be utilized effectively.
On the other hand, the second interconnection of the test signal system is designed automatically depending on the first interconnection of the normal signal system which is designed automatically. As a result, the second interconnection is dependent on the kind or model of the semiconductor integrated circuit device, and the second interconnection must be designed for each kind or model of the semiconductor integrated circuit. Therefore, there are problems in that the interconnection must be drawn around wastefully and that it takes a long time to design and manufacture the semiconductor integrated circuit device.
Furthermore, because the second interconnection of the test signal system differs for each kind or model of the semiconductor integrated circuit, the propagation time of the test signal differs for each kind or model when testing the RAM of the semiconductor integrated circuit. Thus, there is a problem in that an evaluation test such as evaluating the access time of the RAM cannot be carried out uniformly with respect to the different kinds or models of the semiconductor integrated circuit.